`timescale 1ps/1ps

module Mem_tb (
    
);

reg clk;
reg W,R;
reg [15:0] A,DI;
wire [15:0] DO,Inst;
reg [4:0] PC;

initial begin
    clk = 0;
    forever begin
        #1 clk = ~clk;
    end
end

initial begin
    R = 1;
    A = 16'h1;
    PC = 16'h0;
    #5 $stop;
end

Mem u_Mem(
    .clk  (clk  ),
    .W    (W    ),
    .R    (R    ),
    .DI   (DI   ),
    .A    (A    ),
    .DO   (DO   ),
    .PC   (PC   ),
    .Inst (Inst )
);

    
endmodule